LAGE RAHO ELECTRONIC’S ENGINEERS
It is very interesting to see the profession of Medicine being used as a theme in the movie “Munna-Bhai MBBS”.
It is so apparent from the real life in India for engineers that this doesn’t even need a movie to be made because of the kind of choices our young graduating engineers are making at present to get into employment. The subjects you learn and the jobs you do doesn’t have a relation in most of the jobs, not to just blame the engineers, the demand in the outsourced jobs, is a part of the reason. Fortunate thing being electronics engineers not building the fly-overs and the civil engineers not doing the integrated circuit design, though there are exceptions everywhere.
Take the example of an Electronics Engineer who can get absorbed even well before he finishes his last semester by a company, which can mould him into their required skills.
Looking at the developments that are happening in India in the last few years in the semiconductor industry, employers complaining about the shortage of the skilled VLSI engineers (analog and digital) and the students looking for jobs even before they finish their final year and the academia still thinking of upgrading the implementation of the practical skills as part of their curriculum, it looks like a “chicken or the egg problem” for the industry and colleges (you teach us “from colleges” and your learn “from Industry). The I.C design itself being as complex as other disciplines, individual majors should be addressed by the people with expertise in implementing/designing the I.C’s.
You can divide the art of chip design into roughly two categories like front-end and back-end, and each of them in turn can be divided into Analog, Digital and Mixed signal designs etc.. FPGA (Field Programmable Gate Array) on the other hand are slower than their ASIC (Application Specific Integrated Circuit) counterparts and draw more power.
FPGA’s have an advantage of shorter Time To Market, can be reprogrammed and hence are easy to fix the bugs without throwing the device (just re-program it again) so the non-recurring costs are lower. They are also used for prototyping, before making a decision to go on to an ASIC.
ASIC on the other hand is customized for a particular use. Modern ASIC’s consists of number of blocks (that were ASIC’s by themselves in the past) which makes a system on a chip, also called an SOC. ASIC design needs more time because of their complexity and also needs tools that drive the design from the HDL (Hardware Description Language) to a polygon shaped database called GDS2. Tools are supplied from the EDA (Electronic Design Automation) companies like Cadence, Synopsys, Mentor Graphics etc.. Looking at all these, you can derive that “Idea+Talent+Tools(software)+Hardware(machines)” gives the ability to design ASIC’s
Idea comes from the technologists (Architects), Tools come from EDA vendors, Hardware comes from System companies (Wipro,Hcl, Dell, HP etc..), Talent has to come from individuals from the respective disciplines from engineering colleges. There are efforts coming from both the academia and the Industry in tackling this issue and it needs more pace and momentum to reach the required potential, only when the individuals get awareness of their field during their education so that they can sharpen their skills with Finishing School Programs whose aim should be to groom them with concepts and the practical experience that fills the gap between the colleges and the industry.
Are we all ready to watch “Munna-Bhai MicroElectronics” ?
Shashi.Deshpande
Manager
TIIT/ TTM Inc.
www.tiit.in
www.time2mkt.com
Tuesday, December 25, 2007
Friday, October 5, 2007
VLSI Training @ TTM Institute of Information technology (TIIT)
What is TIIT?
TTM Institute of Information Technology (TIIT) is a wholly owned subsidiary of Time To Market Inc, U.S.A. Since 1999, TIIT has trained more than 600 VLSI professionals. TIIT has partnered with University of California Extension, Santa Cruz (UCSC Extension), U.S.A., and Cadence Design Systems (I) Pvt. Ltd.
Why should I consider joining TIIT?
You will be working on licensed version of Cadence tools RTL- GDS2 with faculty around 10+ years experience teaching the courses. The curriculum is designed by experience working professionals, endorsed by University of California Extension and Cadence Design Systems. The course material is constantly updated, with the latest tool versions.
What are the different certification programs you are offering?
1.) Logic Design (Front-end) and 2.) Layout design (Back-end).
Where are you located?
We are located in Hyderabad, Bangalore and starting our new center in Delhi in the month of Sept. 2007
What are the minimum qualifications for the above certification programs?
Prerequisite: BE/BTech/ME/MTech/MSc in either computer science or Electrical/Electronics engineering.
What is the selection procedure?
Screening Test: You have to take screening test that comprises of basic digital electronics & Aptitude (multiple choice).
Can I pay the fee in equal installments?
You can pay the fee in 3 Installments. (40%,30%,30%)
What courses do you offer in front-end and back-end programs?
Front-end program includes courses like Logic-Synthesis, Static Timing Analysis, Digital Design using verilog, Advanced Synthesis Techniques, Design For Test (DFT), System Verilog, Introduction to Formal Verification, Introduction to Lowpower design.
Backend program includes courses like Logic- Synthesis, Static Timing Analysis, Doing custom layouts using Virtuoso, Physical Verification using Assura, Encounter Floorplanning/Placement/Clock-Tree-Synthesis, Nanoroute Router, Celtic Cross Talk Analysis tool and VoltageStorm IR drop tool for SOC system Integrity and last but not the least Introduction to Lowpower layout techniques.
In addition to the above course, we have two core courses for both the programs, 1.) VLSI and ASIC design introduction 2.) VLSI engineering Fundamentals.
What is the history of placements so far?
Placement assistance is provided, which includes preparing for seminars, software engineering required for VLSI engineers, resume making, conducting mock interviews soon after finishing the project.
90% of the trainees got employment so far in the period of 6 –12 months from graduation, in companies like PMC-Sierra, Wipro, Cadence design systems, Cypress Semconductor, TTM Inc. TIIT etc...
Can working people do this course? How?
Yes, because the tool related classes being conducted during weekends there is ample opportunity for working people also to join this course. Labs are open for 20 hrs a day (Morning 6 to 12 Midnight). 85% of the course work will be hands on tools.
What is the Duration of the course?
20 weeks (Intensive).
Which educational institutions or companies recognize/certify the training that you provide?
Our training programs are certified by University of California Extension, Santa Cruz (UCSC Extension) U.S.A. (www.ucsc.edu), and Cadence Design Systems (I) Pvt. Ltd (www.cadence.com). world's leading EDA technology and engineering services company.
Is the curriculum Industry-relevant?
Yes. We offer the Industry oriented, most advanced & researched VLSI Syllabus according to the need of IC design industry, that provides the students, opportunities to choose a career path to suit their core competence.
Is the Library well equipped and sufficient for all the students?
Yes, our library has a good collection of books related to VLSI design and concepts. The library is open from 6:00AM to Midnight.We continuously add the books and update the library
When batch will Starts?
Every 4 months we will start new batch, our intake is 20 seats per batch.
Do we need to book seat in advance?
Yes, by sending 10k DD in advance in favor of
“TTM Institute of Information Technology Pvt Ltd” you can confirm your seat for up-coming batches.
Hurry-up Register your name online today itself at:
TTM Institute of Information Technology (TIIT) is a wholly owned subsidiary of Time To Market Inc, U.S.A. Since 1999, TIIT has trained more than 600 VLSI professionals. TIIT has partnered with University of California Extension, Santa Cruz (UCSC Extension), U.S.A., and Cadence Design Systems (I) Pvt. Ltd.
Why should I consider joining TIIT?
You will be working on licensed version of Cadence tools RTL- GDS2 with faculty around 10+ years experience teaching the courses. The curriculum is designed by experience working professionals, endorsed by University of California Extension and Cadence Design Systems. The course material is constantly updated, with the latest tool versions.
What are the different certification programs you are offering?
1.) Logic Design (Front-end) and 2.) Layout design (Back-end).
Where are you located?
We are located in Hyderabad, Bangalore and starting our new center in Delhi in the month of Sept. 2007
What are the minimum qualifications for the above certification programs?
Prerequisite: BE/BTech/ME/MTech/MSc in either computer science or Electrical/Electronics engineering.
What is the selection procedure?
Screening Test: You have to take screening test that comprises of basic digital electronics & Aptitude (multiple choice).
Can I pay the fee in equal installments?
You can pay the fee in 3 Installments. (40%,30%,30%)
What courses do you offer in front-end and back-end programs?
Front-end program includes courses like Logic-Synthesis, Static Timing Analysis, Digital Design using verilog, Advanced Synthesis Techniques, Design For Test (DFT), System Verilog, Introduction to Formal Verification, Introduction to Lowpower design.
Backend program includes courses like Logic- Synthesis, Static Timing Analysis, Doing custom layouts using Virtuoso, Physical Verification using Assura, Encounter Floorplanning/Placement/Clock-Tree-Synthesis, Nanoroute Router, Celtic Cross Talk Analysis tool and VoltageStorm IR drop tool for SOC system Integrity and last but not the least Introduction to Lowpower layout techniques.
In addition to the above course, we have two core courses for both the programs, 1.) VLSI and ASIC design introduction 2.) VLSI engineering Fundamentals.
What is the history of placements so far?
Placement assistance is provided, which includes preparing for seminars, software engineering required for VLSI engineers, resume making, conducting mock interviews soon after finishing the project.
90% of the trainees got employment so far in the period of 6 –12 months from graduation, in companies like PMC-Sierra, Wipro, Cadence design systems, Cypress Semconductor, TTM Inc. TIIT etc...
Can working people do this course? How?
Yes, because the tool related classes being conducted during weekends there is ample opportunity for working people also to join this course. Labs are open for 20 hrs a day (Morning 6 to 12 Midnight). 85% of the course work will be hands on tools.
What is the Duration of the course?
20 weeks (Intensive).
Which educational institutions or companies recognize/certify the training that you provide?
Our training programs are certified by University of California Extension, Santa Cruz (UCSC Extension) U.S.A. (www.ucsc.edu), and Cadence Design Systems (I) Pvt. Ltd (www.cadence.com). world's leading EDA technology and engineering services company.
Is the curriculum Industry-relevant?
Yes. We offer the Industry oriented, most advanced & researched VLSI Syllabus according to the need of IC design industry, that provides the students, opportunities to choose a career path to suit their core competence.
Is the Library well equipped and sufficient for all the students?
Yes, our library has a good collection of books related to VLSI design and concepts. The library is open from 6:00AM to Midnight.We continuously add the books and update the library
When batch will Starts?
Every 4 months we will start new batch, our intake is 20 seats per batch.
Do we need to book seat in advance?
Yes, by sending 10k DD in advance in favor of
“TTM Institute of Information Technology Pvt Ltd” you can confirm your seat for up-coming batches.
Hurry-up Register your name online today itself at:
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